1. Field of the Invention
The present invention relates to technologies for sampling analog signals and, in particular, to a track and hold circuit.
2. Related Art
The principle underlying digital signal processing is that of sampling the analog signal. A typical situation in which this occurs is in connection with providing digital representations of amplitude values of an analog voltage signal, i.e., analog-to-digital conversion.
For such conversions, a succession of amplitude values of a varying analog signal is selected for conversion to digital representations, each such amplitude value being acquired after a selected interval has elapsed since the preceding acquisition. Often, the best conversion result can be provided if the input signal to the converter maintains a substantially constant value at the input to the analog-to-digital converter during the conversion process.
One type of circuit for providing for a selected duration of time, a substantially constant value for each of the selected analog values is a track-and-hold amplifier. High-speed track-and-hold amplifiers in npn bipolar technologies have achieved very high sampling rates.
One technique using bipolar devices in a high-speed track-and-hold amplifier is explained in Design of a 100-MHz 10-mW 3-V Sample-and Hold Amplifier in Digital Bipolar Technology, IEEE Journal of Solid-State Circuits, Vol. 30, No. 7, July 1983, pp. 724-730, and U.S. Pat. No. 5,298,801, which are incorporated herein by reference. This article and patent disclose a low-voltage open-loop track-and-hold amplifier circuit using all-npn digital bipolar technologies. This track-and-hold amplifier is illustrated in FIG. 1.
The track-and-hold amplifier circuit 100 is a differential circuit in which a differential switching stage SS is coupled at one side to a differential input stage IS having input terminals 11, 21 for receiving a differential input signal Vin1-Vin2. At the other side, switching stage SS is coupled to a differential output stage OS having output terminals 12, 22 for supplying a differential output signal Vout1-Vout2. Differential switching stage SS comprises two similarly constructed sections. The first section of differential switching stage SS comprises a switching transistor Q5 having a base coupled to the input stage IS, a collector coupled to a voltage supply VCC, and an emitter coupled to output stage OS. In addition, the first section of differential switching stage SS comprises a differential amplifier Q8/Q7 which has a first input for receiving a hold signal CK' (CK bar), a second input for receiving a track signal CK, and a common terminal coupled to current source IF. In this way, differential amplifier Q8/Q7 couples current source IF to switching transistor Q5, and switches current from current source IF by the track and hold signals CK, CK'. When current from current source IF is switched through transistor Q7, then transistor Q5 is biased on and forms a simple emitter-follower between input stage IS and a hold capacitor C.sub.H1, coupled between the emitter of switching transistor Q5 and circuit ground. This state is referred to as the track-mode as the output signal at hold capacitor C.sub.H1 will track the input signal.
The second section of the differential switching stage SS comprises a switching transistor Q6 having a base coupled to the input stage IS, a collector coupled to the voltage supply VCC, and an emitter coupled to the output stage OS. In addition, the second section of the differential switching stage SS comprises a differential amplifier Q9/Q10 having a first input for receiving a hold signal CK', a second input for receiving a track signal CK and a common terminal coupled to circuit ground by means of current source IF. Differential amplifier also includes a first output coupled to the base of switching transistor Q6 and a second output coupled to the emitter of the switching transistor Q6. A hold capacitor C.sub.H2 is coupled between the emitter of switching transistor Q6 and circuit ground.
Input stage IS comprises a degenerated differential amplifier Q1/Q2/R1/R2 to supply a signal to the bases of switching transistors Q5, Q6, which signal is related to differential input signal Vin1-Vin2 applied to the input terminals. Degenerated differential amplifier Q1/Q2/R1/R2 has first and second inputs respectively coupled to input terminals 11, 12 for receiving differential input signal Vin1-Vin2, a common terminal coupled to circuit ground by means of a current source IEE, and has first and second outputs coupled to the bases of the respective switching transistors Q5, Q6. The differential amplifier is constructed by means of two npn transistors Q1, Q2 and two emitter resistors R1, R2, and the respective load impedances each comprising resistors R3, R4 respectively arranged in series with diode-connected transistors Q3, Q4, respectively. Distortion introduced by differential amplifier Q1/Q2/R1/R2 is compensated for by the base-emitter junctions in unidirectional diode-coupled transistors Q3 and Q4. As a result of these diode-coupled transistors Q3 and Q4, input stage IS provides a substantially linear voltage-to-voltage conversion.
Track-and-hold amplifier circuit 100 operates as follows. Differential amplifier Q1/Q2/R1/R2 converts differential input signal Vin1-Vin2 applied to input stage IS into a differential voltage drive for switching stage SS.
The mode set by switching stage SS can be a tracking mode or a hold mode. In the track mode, switching transistors Q5, Q6 are in the conductive state as a result of the track signal CK applied to differential amplifiers Q8/Q7, Q9/Q10. In the hold mode, switching transistors Q5 and Q6 are in a cut-off mode as a result of the hold signal CK' applied to differential amplifiers Q8/Q7, Q9/Q1O. As a result of the state of switching transistors Q5, Q6, differential output signal Vout1-Vout2 in the tracking mode is dictated by the input signal. Output signal Vout1-Vout2 in the hold mode is equal to the voltage sampled onto hold capacitors C.sub.H1, C.sub.H2 at the sampling instant, when switching transistors Q5 and Q6 are turned off. In addition, output signal Vout1-Vout2 also includes some finite drooping of this held voltage due to leakage currents in off transistors Q5, Q7, Q6, Q10 and any hold amplifier circuitry which may follow the circuit illustrated in FIG. 1.
Although this track-and-hold amplifier circuit 100 has good switching speed, it has several disadvantages. In practice, when designed for 10-bit linearity, the track-and-hold circuit 100 only accommodates a 1 V differential input swing with a 5 V voltage supply. In addition, the track-and-hold circuit 100 has moderate distortion, much of which is in the amplifier stage. The circuit also suffers from lack of isolation between the signals of the input and the output stages because in the hold mode, input signal Vin1-Vin2 influences output signal Vout1-Vout2. This is referred to as hold-mode feedthrough. This is the feedthrough of the input signal to the hold capacitor C.sub.H1, C.sub.H2 during the hold mode, caused by a parasitic capacitance between the base and the emitter of switching transistors Q5, Q6.
There are various ways that the signal may be fed through to the output. However, the most concerning path is through the capacitance of the base emitter junction of switching transistors Q5, Q6 when these transistors Q5, Q6 are off. As a result, in the hold mode when transistor Q5 is off, for example, the transistor Q5 can be represented as its base-emitter junction capacitance C.sub.je5 . This results in a capacitive divider of the base-emitter capacitance C.sub.je5 of transistor Q5 and hold capacitor C.sub.H1, as illustrated in FIG. 2. However, even though switching transistor Q5 is off, there is still a portion of the input signal Vin1 at node N1. Now the switching on of transistor Q8 has lowered the dc level at the base at transistor Q5, but the impedance at the base of transistor Q5 is the same in the track or hold mode. Thus, the nominal signal amplitude is still present at the base of transistor Q5. As a result, track-and-hold amplifier circuit 100 has poor isolation when it is in the hold mode.
U.S. Pat. No. 5,298,801 discloses one method of reducing the problem of hold-mode feedthrough, which is illustrated in track-and-hold circuit 300 of FIG. 3. Hold-mode feedthrough can be substantially compensated for by providing the track-and-hold circuit with a first and a second feedforward capacitor C.sub.F1 and C.sub.F2, respectively. The first feedforward capacitor C.sub.F1 is coupled between the emitter of one switching transistor Q5 and the base of the other switching transistor Q7. The second feedforward capacitor C.sub.F2 is coupled between the emitter of the other switching transistor Q7 and the base of one switching transistor Q5. The hold-mode feedthrough caused by the parasitic capacitance is compensated for in that feedforward capacitors C.sub.F1, C.sub.F2 receive a drive opposite to the drive of the parasitic capacitance between the base and emitter of switching transistor Q5, Q7. The hold-mode feedthrough can be substantially compensated for when the feedforward capacitors are selected to be identical to the parasitic base-emitter capacitance of the switching transistors Q5, Q7.
One disadvantage to using such feedforward capacitors C.sub.F1, C.sub.F2, however, is that complementary signals Vin1, Vin2 must be available. Therefore, the configuration of track-and-hold circuit 300 is dependent upon having the signal at node N1 move in the exact opposite phase as the signal at node N2. Such complementary signals may not be available if input signals Vin1, Vin2 are provided by an external source or if to conserve power, only half of track-and-hold circuit 300 is constructed. In addition, at high frequencies the input signal may not be exactly complementary which can cause problem with track-and-hold circuit 300. Furthermore, track-and-hold circuit 300 also requires additional power and die space to operate both differential stages.
Therefore, a need exits for a track-and-hold circuit capable of minimizing hold-mode feedthrough without requiring complementary signals.